Huawei’s Top Chip Scientist Says Nvidia Is Running Out of Room to Grow

Huawei’s chief semiconductor scientist has made a rare public case that Nvidia’s chip-scaling strategy is approaching a physical dead end, adding a fresh voice to a long-simmering debate over how much bigger AI processors can realistically get.

Liao Heng, Huawei’s Chief Scientist of Semiconductors and a Fellow at HiSilicon, laid out the argument during a marathon four-hour interview streamed in China in late July. The appearance, first detailed in a Bloomberg report carried by The Star, was one of Huawei’s most direct public statements yet on where it believes Western chipmaking is headed.

Nvidia has spent recent generations pushing two levers at once: larger compute dies packed with billions of transistors, and more stacks of high-bandwidth memory, or HBM, wired around them. Liao argued that approach has a ceiling. “There has to be a limit in how they scale up with ever-increasing compute die and more HBM,” he said. “The industry is still pushing, but once they cross that physical limit, there will be an avalanche.”

His comments echo concerns already circulating among chip foundries. TSMC and Intel, along with Samsung Electronics, all face mounting difficulty shrinking transistors further, even with access to ASML’s advanced extreme ultraviolet lithography tools, the equipment Huawei has been barred from buying under US sanctions.

That restriction is precisely why Huawei went looking for a different route. The company’s answer, a framework it calls the Tau Scaling Law, was first unveiled in May by He Tingbo, president of Huawei’s semiconductor division, at the IEEE International Symposium on Circuits and Systems in Shanghai. Rather than shrinking transistors, it optimises for how quickly signals move across a chip. The first commercial product built on the idea, a vertically stacked design called LogicFolding, is due to appear in Huawei’s next Kirin smartphone chip this autumn.

Liao also used the interview to praise DeepSeek founder Liang Wenfeng, crediting the AI lab’s resource-constrained model architecture for triggering last year’s multibillion-dollar selloff in AI stocks. He described Chinese AI development as making the most of a cramped apartment while rivals work in a spacious villa, and said Huawei is now designing chips through a “co-design” approach meant to trade added complexity for lower compute demand.

Beyond the technical claims, Liao framed the moment in geopolitical terms. “To survive, each side has to build its own complete manufacturing and supply capabilities, even without serious clashes between the two sides,” he said, describing a chip industry splitting into two increasingly separate ecosystems.

Independent verification is still months away. Analysts at firms including SemiAnalysis and TechInsights are expected to tear down Huawei’s new Kirin chip once it ships, which will offer the first real test of whether LogicFolding delivers on its claims.

Our Take

Liao’s comments are notable less for the physics, which chip engineers have debated for years, and more for the confidence behind them. A company still years removed from EUV access is now framing its constraint as a design philosophy rather than a limitation, and putting a named chief scientist on record to say so.

That said, the real test isn’t a podcast. It’s the teardown. Huawei has made bold claims about Tau Scaling before delivering the silicon to back them up, and this autumn’s Kirin launch is the first hard checkpoint. Until independent labs get their hands on it, Liao’s “avalanche” is a prediction, not a measurement.

What is measurable already is the shift in posture. Whether or not Nvidia hits a wall on schedule, Huawei is no longer talking like a company playing catch-up. That framing, on its own, is worth watching as closely as the chip itself.